1. Field of the Invention
The present invention relates generally to an input data processing circuit adapted to process input data sets received from doubled circuits which are asynchronous with each other.
2. Description of the Related Art
Generally, a system with high reliability comprises redundant doubled circuits, for example, a primary circuit and a redundant circuit, which have the same structure. In a system, clocks, data, enable signals are supplied from the doubled circuits of upper level to a lower level circuit.
In a design phase, clocks are determined so as to be equal in rate to each other between doubled circuits. In actual, a fabrication process however causes the clocks to have some “ppm” margin of error. That is, one of the clocks becomes slightly lower than the other clock. Therefore, it is desirable to intend to design a system where both clocks are asynchronous with or independent of each other.
To suitably receive input data sets according to the asynchronous clocks, the lower level circuit comprises an input data processing circuit at an input stage of the lower level circuit. An input data processing circuit known to the inventor comprises two FIFO (first-in first-out) buffers and a readout circuitry. The FIFO buffers correspond to the doubled circuits, and temporally store input data sets in compliance with the clocks supplied from the doubled circuits, respectively. The readout circuitry generates a common readout clock, and reads input data sets out of the FIFO buffers according to the common readout clock.
However, the fabrication error occurring between clocks of the doubled circuits might cause “data lack” in anyone of the FIFO buffers. As mentioned above, one of the clocks generated by the doubled circuits is slightly lower than the other clock, so that data storing in the FIFO buffer corresponding to the slightly lower clock is delayed in comparison with data storing in the other FIFO buffer. In addition, because the readout clock is single, the delay of data storing corresponding to the difference between both clocks accumulates, as the number of readout clocks increases. Eventually, the data lack therefore occurs in the FIFO buffer corresponding to the slightly lower clock.
As apparent from the above description, a need exists for an input data processing circuit that is tolerant to a clock rate difference between clocks generated by the doubled circuits, respectively, and that can avoid “data lack.”